D flip flop
D-type flip flop
Data or delay flip flop is a modified clock RS flip flop that has a single data input in addition to a clock input. The D input directly goes to the S input and the complement is applied to the R input through the NOT gate.
It prevents the value of D from reaching the output until a clock pulse occurs.
Truth table for D flip flop
| S | R | Q(t+1) |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
Excitation table for D flip flop
| S | Q |
| 0 | 0 |
| 1 | 1 |
Reference