JK flip flops

The features of the JK flip flops are as follows:

1. If J&K inputs are 1, and a clock pulse is applied then the output will change state, regardless of its previous state.
2. When J&K both inputs are zero, and the clock pulse is applied then the output will have no change.

When J=0 and K=0,

The NAND gate is disabled, hence the clock pulse has no effect on the flip flop.

When J=1 and K=0,

The lower NAND gate is disabled and the upper NAND gate is enabled. 

When J=0 and K=1,

The upper NAND gate is disabled and the lower NAND gate is enabled.

When J=1 and K=1,

If the Q=0 the lower NAND gate gets diabled, if Q=1 the upper NAND gate gets disabled. 

Reference

JK flip flops